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[/] [amber/] [trunk/] [hw/] - Rev 71

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71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4039d 02h /amber/trunk/hw/
70 The mlas_bug testcase tried to use stack without setting stack pointer
register, causing unpredictable behavoiur.
The patch uses an expilict stack area for the test.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4039d 02h /amber/trunk/hw/
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4039d 03h /amber/trunk/hw/
67 renamed boot-loader.c to boot-loader-serial.c csantifort 4039d 03h /amber/trunk/hw/
64 Support latest Xilinx ISE 14.5 software. csantifort 4039d 03h /amber/trunk/hw/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4039d 08h /amber/trunk/hw/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.		 csantifort 4326d 02h /amber/trunk/hw/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4543d 22h /amber/trunk/hw/
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4613d 20h /amber/trunk/hw/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4613d 23h /amber/trunk/hw/
57 Add some debug messages csantifort 4613d 23h /amber/trunk/hw/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.		 csantifort 4613d 23h /amber/trunk/hw/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4630d 23h /amber/trunk/hw/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4645d 21h /amber/trunk/hw/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4645d 21h /amber/trunk/hw/
50 Revert to previous version csantifort 4686d 21h /amber/trunk/hw/
49 Added a note n how to change timeouts csantifort 4686d 21h /amber/trunk/hw/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.		 csantifort 4691d 03h /amber/trunk/hw/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4711d 01h /amber/trunk/hw/
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4718d 23h /amber/trunk/hw/

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