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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_core.v] - Rev 83

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83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3328d 17h /amber/trunk/hw/vlog/amber25/a25_core.v
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4635d 07h /amber/trunk/hw/vlog/amber25/a25_core.v
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 4733d 07h /amber/trunk/hw/vlog/amber25/a25_core.v
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts		 csantifort 4736d 14h /amber/trunk/hw/vlog/amber25/a25_core.v
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.		 csantifort 4821d 13h /amber/trunk/hw/vlog/amber25/a25_core.v
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions		 csantifort 4825d 11h /amber/trunk/hw/vlog/amber25/a25_core.v
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.		 csantifort 4828d 02h /amber/trunk/hw/vlog/amber25/a25_core.v

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