OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_decompile.v] - Rev 87

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
87 Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 csantifort 3315d 12h /amber/trunk/hw/vlog/amber25/a25_decompile.v
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3342d 04h /amber/trunk/hw/vlog/amber25/a25_decompile.v
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4028d 17h /amber/trunk/hw/vlog/amber25/a25_decompile.v
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4603d 08h /amber/trunk/hw/vlog/amber25/a25_decompile.v
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4736d 12h /amber/trunk/hw/vlog/amber25/a25_decompile.v
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions
csantifort 4825d 10h /amber/trunk/hw/vlog/amber25/a25_decompile.v
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.
csantifort 4828d 00h /amber/trunk/hw/vlog/amber25/a25_decompile.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.