URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_execute.v] - Rev 82

Rev	Log message	Author	Age	Path
82	Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug	csantifort	3342d 08h	/amber/trunk/hw/vlog/amber25/a25_execute.v
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4620d 12h	/amber/trunk/hw/vlog/amber25/a25_execute.v
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4635d 10h	/amber/trunk/hw/vlog/amber25/a25_execute.v
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4736d 17h	/amber/trunk/hw/vlog/amber25/a25_execute.v
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	4821d 16h	/amber/trunk/hw/vlog/amber25/a25_execute.v
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	4828d 05h	/amber/trunk/hw/vlog/amber25/a25_execute.v