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Rev Log message Author Age Path
82 correct some typoes, thanks to Hu, Tao wsong0210 3991d 01h /
81 adding a solution in README to a cell lib problem. wsong0210 4359d 01h /
80 make the README file more understandable wsong0210 4438d 21h /
79 update comments in sim compile.sh to clarify that synthesis must be done before post-synthesis simulation wsong0210 4499d 07h /
78 pass link wsong0210 4665d 19h /
77 pass syn elaboration wsong0210 4666d 18h /
76 fix syntex wsong0210 4670d 19h /
75 code finished, start the debugging wsong0210 4670d 19h /
74 in/out buffer finished wsong0210 4671d 19h /
73 input buffer wsong0210 4678d 18h /
72 clos-opt ongoing, Clos switch finished, nxt input buffer wsong0210 4679d 18h /
71 the buffered 2-stage Clos switch wsong0210 4680d 18h /
70 clos-opt ongoing wsong0210 4680d 18h /
69 central module of the Clos wsong0210 4683d 18h /
68 rewite the clos switch in the SDM-Clos-buf router wsong0210 4684d 19h /
67 structure not good, prepare to use new files wsong0210 4684d 20h /
66 clos opt ongoing wsong0210 4699d 13h /
65 pipeline controller wsong0210 4699d 13h /
64 clos opt ongoing wsong0210 4699d 13h /
63 clos opt ongoing wsong0210 4699d 18h /

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