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[/] [ata/] [trunk/] - Rev 33

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Rev	Log message	Author	Age	Path
33	New directory structure.	root	5527d 08h	/ata/trunk/
32	Fixed a potential bug where the core was forced into an unknown state when an asynchronous reset was given without a running clock.	rherveille	8013d 21h	/trunk/
31	Changed internal counter libraries. Split counter.vhd into separate files. Core is in same state as Verilog version now.	rherveille	8093d 00h	/trunk/
30	Fixed data-latch bug (posedge ata_diow instead of negedge ata_diow).	rherveille	8096d 21h	/trunk/
29	no message	rherveille	8103d 13h	/trunk/
28	renamed IO names revised document	rherveille	8103d 13h	/trunk/
27	renamed all files to 'atahost_***.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd'	rherveille	8103d 13h	/trunk/
26	renamed 'atahost.vhd' to 'atahost_top.vhd' renamed 'controller.vhd' to 'atahost_controller.vhd' renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd'	rherveille	8103d 13h	/trunk/
25	renamed 'atahost.vhd' to 'atahost_top.vhd' renamed 'controller.vhd' to 'atahost_controller.vhd' renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd' core is now equivalent to verilog version	rherveille	8103d 13h	/trunk/
24	Initial Verilog HDL release	rherveille	8103d 13h	/trunk/
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8103d 13h	/trunk/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8105d 17h	/trunk/
21	Changed atahost_top pin-information.	rherveille	8105d 17h	/trunk/
20	Some minor bug fixes	rherveille	8219d 13h	/trunk/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8228d 18h	/trunk/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8256d 22h	/trunk/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8262d 19h	/trunk/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8289d 17h	/trunk/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8290d 16h	/trunk/
14	created new directory structure	rherveille	8302d 17h	/trunk/

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[/] [ata/] [trunk/] - Rev 33

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