URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] [ata/] [trunk/] - Rev 33

Rev	Log message	Author	Age	Path
13	no message	rherveille	8314d 15h	/ata/trunk/
12	Fixed some blocking versus non-blocking statement issues.	rherveille	8321d 20h	/ata/trunk/
11	Created directory structure (documentation, vhdl, verilog)	rherveille	8332d 09h	/ata/trunk/
10	- renamed 'ata.vhd' to 'atahost.vhd' - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8337d 10h	/ata/trunk/
9	- renamed 'ata.vhd' to 'atahost.vhd' - Changed PIOreq & PIOack generation (controller.vhd); made them synchronous - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8337d 10h	/ata/trunk/
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8337d 20h	/ata/trunk/
7	no message	rherveille	8339d 07h	/ata/trunk/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8339d 07h	/ata/trunk/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8345d 12h	/ata/trunk/
4	Fixed some incomplete port lists. Fixed some Verilog related issues. Design now compiles completely.	rherveille	8346d 17h	/ata/trunk/