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[/] [ata/] [trunk/] [rtl/] [verilog/] - Rev 33

Rev	Log message	Author	Age	Path
33	New directory structure.	root	5542d 01h	/ata/trunk/rtl/verilog/
32	Fixed a potential bug where the core was forced into an unknown state when an asynchronous reset was given without a running clock.	rherveille	8028d 14h	/ata/trunk/rtl/verilog/
24	Initial Verilog HDL release	rherveille	8118d 06h	/ata/trunk/rtl/verilog/
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8118d 06h	/ata/trunk/rtl/verilog/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8120d 10h	/ata/trunk/rtl/verilog/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8243d 11h	/ata/trunk/rtl/verilog/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8271d 15h	/ata/trunk/rtl/verilog/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8277d 12h	/ata/trunk/rtl/verilog/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8304d 10h	/ata/trunk/rtl/verilog/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8305d 09h	/ata/trunk/rtl/verilog/
14	created new directory structure	rherveille	8317d 10h	/ata/trunk/rtl/verilog/