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[/] - Rev 9

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Rev Log message Author Age Path
9 Added note about Xilinx synthesis isssue with 192 Bit key.
Removed draft-watermark.
ruschi 5184d 18h /
8 added Encryption datapath of aes_core.vhd ruschi 5433d 07h /
7 Included Inner Core section with figure ruschi 5433d 07h /
6 deleted the reference to util_lib which never existed in the opencores version and is not needed ruschi 5433d 07h /
5 added software driver and small test-program I used to check correct function ruschi 5474d 19h /
4 fixed bug in interrupt request gerneration ruschi 5474d 20h /
3 cleanup ruschi 5474d 20h /
2 ruschi 5474d 20h /
1 The project was created and the structure was created root 5478d 09h /

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