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[/] [axi_master] - Rev 21

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Rev Log message Author Age Path
21 revision 1.5 eyalhoc 4716d 11h /axi_master
20 eyalhoc 4728d 10h /axi_master
19 fixed pending for slaves eyalhoc 4729d 10h /axi_master
18 IC give WVALID before AWREADY eyalhoc 4732d 04h /axi_master
17 IC support same ID from different masters eyalhoc 4735d 10h /axi_master
16 RobustVerilog version 1.4 compatible eyalhoc 4736d 03h /axi_master
15 Support RobustVerilog project eyalhoc 4748d 12h /axi_master
14 GUI support eyalhoc 4755d 07h /axi_master
13 eyalhoc 4764d 07h /axi_master
12 create prgen rand eyalhoc 4781d 08h /axi_master
11 support single slave eyalhoc 4781d 13h /axi_master
10 minor fixes eyalhoc 4783d 15h /axi_master
9 add insert_rand task eyalhoc 4786d 15h /axi_master
8 use match signals eyalhoc 4786d 15h /axi_master
7 allow no user bits eyalhoc 4786d 15h /axi_master
6 added check_single and write_and_check_single tasks
added option to random data by address
eyalhoc 4796d 06h /axi_master
5 added dos batch file for windows eyalhoc 4799d 08h /axi_master
4 eyalhoc 4805d 04h /axi_master
3 eyalhoc 4805d 08h /axi_master
2 eyalhoc 4805d 08h /axi_master

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