OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 138

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7404d 02h /
137 Header changed. mohor 7404d 02h /
136 Error counters changed. mohor 7404d 02h /
135 Header changed. mohor 7404d 02h /
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7512d 00h /
133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7518d 11h /
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7518d 11h /
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7518d 11h /
130 mbist signals updated according to newest convention markom 7518d 11h /
129 Error counters changed. mohor 7534d 19h /
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7534d 20h /
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7534d 20h /
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7535d 16h /
125 Synchronization changed, error counters fixed. mohor 7539d 22h /
124 ALTERA_RAM supported. mohor 7560d 04h /
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7567d 09h /
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7567d 09h /
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7567d 09h /
120 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7576d 06h /
119 Artisan RAMs added. mohor 7576d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.