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Rev Log message Author Age Path
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7299d 21h /
140 I forgot to thange one signal name. igorm 7354d 20h /
139 Signal bus_off_on added. igorm 7354d 20h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7393d 22h /
137 Header changed. mohor 7393d 23h /
136 Error counters changed. mohor 7393d 23h /
135 Header changed. mohor 7393d 23h /
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7501d 20h /
133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7508d 07h /
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7508d 07h /
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7508d 07h /
130 mbist signals updated according to newest convention markom 7508d 07h /
129 Error counters changed. mohor 7524d 16h /
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7524d 16h /
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7524d 16h /
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7525d 12h /
125 Synchronization changed, error counters fixed. mohor 7529d 18h /
124 ALTERA_RAM supported. mohor 7550d 01h /
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7557d 06h /
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7557d 06h /

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