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[/] - Rev 143

Rev	Log message	Author	Age	Path
143	Bit acceptance_filter_mode was inverted.	igorm	7279d 16h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7298d 15h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7298d 15h	/
140	I forgot to thange one signal name.	igorm	7353d 13h	/
139	Signal bus_off_on added.	igorm	7353d 14h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7392d 16h	/
137	Header changed.	mohor	7392d 16h	/
136	Error counters changed.	mohor	7392d 16h	/
135	Header changed.	mohor	7392d 17h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7500d 14h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7507d 01h	/
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7507d 01h	/
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7507d 01h	/
130	mbist signals updated according to newest convention	markom	7507d 01h	/
129	Error counters changed.	mohor	7523d 10h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7523d 10h	/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7523d 10h	/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7524d 06h	/
125	Synchronization changed, error counters fixed.	mohor	7528d 12h	/
124	ALTERA_RAM supported.	mohor	7548d 18h	/