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[/] - Rev 147

Rev	Log message	Author	Age	Path
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7131d 19h	/
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7132d 01h	/
145	Arbitration bug fixed.	igorm	7132d 01h	/
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7278d 16h	/
143	Bit acceptance_filter_mode was inverted.	igorm	7278d 16h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7297d 15h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7297d 15h	/
140	I forgot to thange one signal name.	igorm	7352d 13h	/
139	Signal bus_off_on added.	igorm	7352d 14h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7391d 16h	/
137	Header changed.	mohor	7391d 17h	/
136	Error counters changed.	mohor	7391d 17h	/
135	Header changed.	mohor	7391d 17h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7499d 14h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7506d 01h	/
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7506d 01h	/
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7506d 01h	/
130	mbist signals updated according to newest convention	markom	7506d 01h	/
129	Error counters changed.	mohor	7522d 10h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7522d 10h	/