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Rev	Log message	Author	Age	Path
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7145d 03h	/
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7145d 09h	/
145	Arbitration bug fixed.	igorm	7145d 09h	/
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7292d 00h	/
143	Bit acceptance_filter_mode was inverted.	igorm	7292d 00h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7310d 23h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7310d 23h	/
140	I forgot to thange one signal name.	igorm	7365d 22h	/
139	Signal bus_off_on added.	igorm	7365d 22h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7405d 00h	/
137	Header changed.	mohor	7405d 01h	/
136	Error counters changed.	mohor	7405d 01h	/
135	Header changed.	mohor	7405d 01h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7512d 22h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7519d 09h	/
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7519d 09h	/
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7519d 09h	/
130	mbist signals updated according to newest convention	markom	7519d 09h	/
129	Error counters changed.	mohor	7535d 18h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7535d 18h	/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7535d 18h	/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7536d 14h	/
125	Synchronization changed, error counters fixed.	mohor	7540d 20h	/
124	ALTERA_RAM supported.	mohor	7561d 02h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7568d 08h	/
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7568d 08h	/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7568d 08h	/
120	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7577d 05h	/
119	Artisan RAMs added.	mohor	7577d 05h	/
118	Artisan RAM fixed (when not using BIST).	mohor	7577d 05h	/

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