OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 158

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 Fixing overrun problems. igorm 6866d 01h /
157 In "Extended mode" when dual filter was used and standard frame received,
upper nibble of the data was not filtered ok.		 igorm 6959d 22h /
156 Wake-up interrupt was generated in some cases. igorm 6980d 20h /
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 6989d 03h /
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7088d 20h /
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7096d 16h /
152 Fixes for compatibility after the SW reset. igorm 7100d 22h /
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7103d 17h /
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7122d 16h /
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7122d 16h /
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7124d 23h /
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7124d 23h /
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7125d 04h /
145 Arbitration bug fixed. igorm 7125d 04h /
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7271d 20h /
143 Bit acceptance_filter_mode was inverted. igorm 7271d 20h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7290d 19h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7290d 19h /
140 I forgot to thange one signal name. igorm 7345d 17h /
139 Signal bus_off_on added. igorm 7345d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.