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[/] - Rev 163

Rev	Log message	Author	Age	Path
143	Bit acceptance_filter_mode was inverted.	igorm	7277d 05h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7296d 04h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7296d 04h	/
140	I forgot to thange one signal name.	igorm	7351d 02h	/
139	Signal bus_off_on added.	igorm	7351d 02h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7390d 05h	/
137	Header changed.	mohor	7390d 05h	/
136	Error counters changed.	mohor	7390d 05h	/
135	Header changed.	mohor	7390d 05h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7498d 03h	/