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Rev Log message Author Age Path
161 New directory structure. root 5536d 15h /can/tags/rel_17/
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7556d 04h /tags/rel_17/
118 Artisan RAM fixed (when not using BIST). mohor 7565d 01h /trunk/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7565d 01h /trunk/
115 Artisan ram instances added. simons 7570d 19h /trunk/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7597d 19h /trunk/
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7599d 19h /trunk/
110 Fixed according to the linter. mohor 7599d 20h /trunk/
109 Fixed according to the linter. mohor 7599d 21h /trunk/
108 Fixed according to the linter. mohor 7599d 21h /trunk/
107 Fixed according to the linter. mohor 7599d 21h /trunk/
106 Unused signal removed. mohor 7605d 19h /trunk/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7606d 09h /trunk/
102 Little fixes (to fix warnings). mohor 7608d 23h /trunk/
100 Synchronization changed. mohor 7613d 01h /trunk/
99 PCI_BIST replaced with CAN_BIST. mohor 7613d 01h /trunk/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7618d 13h /trunk/
95 Virtual silicon ram instances added. simons 7618d 14h /trunk/
93 synthesis full_case parallel_case fixed. mohor 7624d 01h /trunk/
92 clkout is clk/2 after the reset. mohor 7624d 09h /trunk/

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