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[/] [can/] [tags/] [rel_18/] [bench/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5557d 10h /can/tags/rel_18/bench/
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7544d 09h /can/tags/rel_18/bench/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7544d 09h /can/tags/rel_18/bench/
119 Artisan RAMs added. mohor 7585d 20h /can/tags/rel_18/bench/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7649d 15h /can/tags/rel_18/bench/
68 CAN inturrupt is active low. mohor 7732d 19h /can/tags/rel_18/bench/
63 ALE changes on negedge of clk. mohor 7744d 10h /can/tags/rel_18/bench/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.
mohor 7747d 00h /can/tags/rel_18/bench/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.
mohor 7747d 01h /can/tags/rel_18/bench/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.
mohor 7747d 02h /can/tags/rel_18/bench/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7753d 15h /can/tags/rel_18/bench/
50 Top level signal names changed. mohor 7753d 15h /can/tags/rel_18/bench/
48 Actel APA ram supported. mohor 7757d 07h /can/tags/rel_18/bench/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7767d 15h /can/tags/rel_18/bench/
38 Temporary backup version (still fully operable). mohor 7769d 06h /can/tags/rel_18/bench/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7769d 06h /can/tags/rel_18/bench/
35 Several registers added. Not finished, yet. mohor 7772d 10h /can/tags/rel_18/bench/
34 Errors monitoring improved. arbitration_lost improved. mohor 7774d 16h /can/tags/rel_18/bench/
31 Wishbone interface added. mohor 7776d 05h /can/tags/rel_18/bench/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.
mohor 7777d 11h /can/tags/rel_18/bench/

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