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[/] [can/] [tags/] [rel_21/] [rtl/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5558d 15h /can/tags/rel_21/rtl/
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7301d 20h /can/tags/rel_21/rtl/
143 Bit acceptance_filter_mode was inverted. igorm 7301d 20h /can/tags/rel_21/rtl/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7320d 19h /can/tags/rel_21/rtl/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7414d 20h /can/tags/rel_21/rtl/
137 Header changed. mohor 7414d 20h /can/tags/rel_21/rtl/
136 Error counters changed. mohor 7414d 20h /can/tags/rel_21/rtl/
135 Header changed. mohor 7414d 20h /can/tags/rel_21/rtl/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7522d 18h /can/tags/rel_21/rtl/
130 mbist signals updated according to newest convention markom 7529d 05h /can/tags/rel_21/rtl/
129 Error counters changed. mohor 7545d 13h /can/tags/rel_21/rtl/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7546d 10h /can/tags/rel_21/rtl/
125 Synchronization changed, error counters fixed. mohor 7550d 16h /can/tags/rel_21/rtl/
124 ALTERA_RAM supported. mohor 7570d 22h /can/tags/rel_21/rtl/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7578d 04h /can/tags/rel_21/rtl/
118 Artisan RAM fixed (when not using BIST). mohor 7587d 01h /can/tags/rel_21/rtl/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7587d 01h /can/tags/rel_21/rtl/
115 Artisan ram instances added. simons 7592d 18h /can/tags/rel_21/rtl/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7619d 19h /can/tags/rel_21/rtl/
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7621d 19h /can/tags/rel_21/rtl/

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