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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5536d 20h	/can/tags/rel_23/
148	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7133d 04h	/tags/rel_23/
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7133d 04h	/trunk/
145	Arbitration bug fixed.	igorm	7133d 09h	/trunk/
143	Bit acceptance_filter_mode was inverted.	igorm	7280d 01h	/trunk/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7299d 00h	/trunk/
140	I forgot to thange one signal name.	igorm	7353d 22h	/trunk/
139	Signal bus_off_on added.	igorm	7353d 22h	/trunk/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7393d 01h	/trunk/
137	Header changed.	mohor	7393d 01h	/trunk/
136	Error counters changed.	mohor	7393d 01h	/trunk/
135	Header changed.	mohor	7393d 01h	/trunk/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7500d 23h	/trunk/
130	mbist signals updated according to newest convention	markom	7507d 10h	/trunk/
129	Error counters changed.	mohor	7523d 18h	/trunk/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7523d 19h	/trunk/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7524d 15h	/trunk/
125	Synchronization changed, error counters fixed.	mohor	7528d 21h	/trunk/
124	ALTERA_RAM supported.	mohor	7549d 03h	/trunk/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7556d 09h	/trunk/

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[/] [can/] [tags/] [rel_23/] - Rev 161

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