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Rev Log message Author Age Path
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7516d 04h /can/trunk/
130 mbist signals updated according to newest convention markom 7522d 15h /can/trunk/
129 Error counters changed. mohor 7539d 00h /can/trunk/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7539d 00h /can/trunk/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7539d 20h /can/trunk/
125 Synchronization changed, error counters fixed. mohor 7544d 02h /can/trunk/
124 ALTERA_RAM supported. mohor 7564d 08h /can/trunk/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7571d 14h /can/trunk/
119 Artisan RAMs added. mohor 7580d 11h /can/trunk/
118 Artisan RAM fixed (when not using BIST). mohor 7580d 11h /can/trunk/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7580d 11h /can/trunk/
115 Artisan ram instances added. simons 7586d 05h /can/trunk/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7613d 05h /can/trunk/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7615d 06h /can/trunk/
110 Fixed according to the linter. mohor 7615d 06h /can/trunk/
109 Fixed according to the linter. mohor 7615d 07h /can/trunk/
108 Fixed according to the linter. mohor 7615d 07h /can/trunk/
107 Fixed according to the linter. mohor 7615d 08h /can/trunk/
106 Unused signal removed. mohor 7621d 05h /can/trunk/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7621d 19h /can/trunk/
102 Little fixes (to fix warnings). mohor 7624d 10h /can/trunk/
100 Synchronization changed. mohor 7628d 11h /can/trunk/
99 PCI_BIST replaced with CAN_BIST. mohor 7628d 11h /can/trunk/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7633d 23h /can/trunk/
95 Virtual silicon ram instances added. simons 7634d 00h /can/trunk/
93 synthesis full_case parallel_case fixed. mohor 7639d 11h /can/trunk/
92 clkout is clk/2 after the reset. mohor 7639d 19h /can/trunk/
90 paralel_case and full_case compiler directives added to case statements. mohor 7640d 09h /can/trunk/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7641d 06h /can/trunk/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7641d 06h /can/trunk/

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