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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5526d 19h	/can/trunk/
160	New tests for testing the bus-off.	igorm	6576d 01h	/trunk/
159	* empty log message *	igorm	6864d 02h	/trunk/
158	Fixing overrun problems.	igorm	6864d 04h	/trunk/
157	In "Extended mode" when dual filter was used and standard frame received, upper nibble of the data was not filtered ok.	igorm	6958d 02h	/trunk/
156	Wake-up interrupt was generated in some cases.	igorm	6979d 00h	/trunk/
155	rd_info_pointer fixed (fifo_empty was used instead of info_empty).	igorm	6987d 06h	/trunk/
154	irq is cleared after the release_buffer command. This bug was entered with changes for the edge triggered interrupts.	igorm	7087d 00h	/trunk/
153	Arbitration capture register changed. SW reset (setting the reset_mode bit) doesn't work as HW reset.	igorm	7094d 19h	/trunk/
152	Fixes for compatibility after the SW reset.	igorm	7099d 02h	/trunk/
151	When CAN was reset by setting the reset_mode signal in mode register, it was possible that CAN was blocked for a short period of time. Problem occured very rarly.	igorm	7101d 20h	/trunk/
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7120d 20h	/trunk/
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7123d 03h	/trunk/
145	Arbitration bug fixed.	igorm	7123d 08h	/trunk/
143	Bit acceptance_filter_mode was inverted.	igorm	7270d 00h	/trunk/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7288d 23h	/trunk/
140	I forgot to thange one signal name.	igorm	7343d 21h	/trunk/
139	Signal bus_off_on added.	igorm	7343d 21h	/trunk/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7383d 00h	/trunk/
137	Header changed.	mohor	7383d 00h	/trunk/
136	Error counters changed.	mohor	7383d 00h	/trunk/
135	Header changed.	mohor	7383d 00h	/trunk/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7490d 22h	/trunk/
130	mbist signals updated according to newest convention	markom	7497d 09h	/trunk/
129	Error counters changed.	mohor	7513d 18h	/trunk/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7513d 18h	/trunk/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7514d 14h	/trunk/
125	Synchronization changed, error counters fixed.	mohor	7518d 20h	/trunk/
124	ALTERA_RAM supported.	mohor	7539d 02h	/trunk/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7546d 08h	/trunk/

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