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[/] [can/] [trunk/] [bench/] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5547d 20h	/can/trunk/bench
160	New tests for testing the bus-off.	igorm	6597d 02h	/trunk/bench
158	Fixing overrun problems.	igorm	6885d 05h	/trunk/bench
140	I forgot to thange one signal name.	igorm	7364d 22h	/trunk/bench
139	Signal bus_off_on added.	igorm	7364d 22h	/trunk/bench
130	mbist signals updated according to newest convention	markom	7518d 09h	/trunk/bench
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7534d 18h	/trunk/bench
119	Artisan RAMs added.	mohor	7576d 05h	/trunk/bench
83	cs_can_i is used only when WISHBONE interface is not used.	mohor	7640d 00h	/trunk/bench
68	CAN inturrupt is active low.	mohor	7723d 04h	/trunk/bench
63	ALE changes on negedge of clk.	mohor	7734d 20h	/trunk/bench
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7737d 09h	/trunk/bench
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7737d 11h	/trunk/bench
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7737d 11h	/trunk/bench
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7744d 00h	/trunk/bench
50	Top level signal names changed.	mohor	7744d 00h	/trunk/bench
48	Actel APA ram supported.	mohor	7747d 16h	/trunk/bench
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7758d 01h	/trunk/bench
38	Temporary backup version (still fully operable).	mohor	7759d 15h	/trunk/bench
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7759d 15h	/trunk/bench

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[/] [can/] [trunk/] [bench/] - Rev 161

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