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[/] [can/] [trunk/] [rtl/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5536d 00h /can/trunk/rtl/
157 In "Extended mode" when dual filter was used and standard frame received,
upper nibble of the data was not filtered ok.		 igorm 6967d 06h /trunk/rtl/
156 Wake-up interrupt was generated in some cases. igorm 6988d 04h /trunk/rtl/
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 6996d 11h /trunk/rtl/
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7096d 04h /trunk/rtl/
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7104d 00h /trunk/rtl/
152 Fixes for compatibility after the SW reset. igorm 7108d 07h /trunk/rtl/
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7111d 01h /trunk/rtl/
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7130d 01h /trunk/rtl/
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7132d 08h /trunk/rtl/
145 Arbitration bug fixed. igorm 7132d 13h /trunk/rtl/
143 Bit acceptance_filter_mode was inverted. igorm 7279d 05h /trunk/rtl/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7298d 03h /trunk/rtl/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7392d 04h /trunk/rtl/
137 Header changed. mohor 7392d 05h /trunk/rtl/
136 Error counters changed. mohor 7392d 05h /trunk/rtl/
135 Header changed. mohor 7392d 05h /trunk/rtl/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7500d 03h /trunk/rtl/
130 mbist signals updated according to newest convention markom 7506d 13h /trunk/rtl/
129 Error counters changed. mohor 7522d 22h /trunk/rtl/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7523d 18h /trunk/rtl/
125 Synchronization changed, error counters fixed. mohor 7528d 00h /trunk/rtl/
124 ALTERA_RAM supported. mohor 7548d 07h /trunk/rtl/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7555d 12h /trunk/rtl/
118 Artisan RAM fixed (when not using BIST). mohor 7564d 09h /trunk/rtl/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7564d 09h /trunk/rtl/
115 Artisan ram instances added. simons 7570d 03h /trunk/rtl/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7597d 04h /trunk/rtl/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7599d 04h /trunk/rtl/
110 Fixed according to the linter. mohor 7599d 04h /trunk/rtl/

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