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[/] [can/] [trunk/] [rtl/] [verilog/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5549d 18h /can/trunk/rtl/verilog/
157 In "Extended mode" when dual filter was used and standard frame received,
upper nibble of the data was not filtered ok.		 igorm 6981d 01h /can/trunk/rtl/verilog/
156 Wake-up interrupt was generated in some cases. igorm 7001d 23h /can/trunk/rtl/verilog/
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 7010d 05h /can/trunk/rtl/verilog/
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7109d 23h /can/trunk/rtl/verilog/
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7117d 19h /can/trunk/rtl/verilog/
152 Fixes for compatibility after the SW reset. igorm 7122d 01h /can/trunk/rtl/verilog/
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7124d 19h /can/trunk/rtl/verilog/
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7143d 19h /can/trunk/rtl/verilog/
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7146d 02h /can/trunk/rtl/verilog/
145 Arbitration bug fixed. igorm 7146d 07h /can/trunk/rtl/verilog/
143 Bit acceptance_filter_mode was inverted. igorm 7292d 23h /can/trunk/rtl/verilog/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7311d 22h /can/trunk/rtl/verilog/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7405d 23h /can/trunk/rtl/verilog/
137 Header changed. mohor 7405d 23h /can/trunk/rtl/verilog/
136 Error counters changed. mohor 7405d 23h /can/trunk/rtl/verilog/
135 Header changed. mohor 7406d 00h /can/trunk/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7513d 21h /can/trunk/rtl/verilog/
130 mbist signals updated according to newest convention markom 7520d 08h /can/trunk/rtl/verilog/
129 Error counters changed. mohor 7536d 17h /can/trunk/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7537d 13h /can/trunk/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7541d 19h /can/trunk/rtl/verilog/
124 ALTERA_RAM supported. mohor 7562d 01h /can/trunk/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7569d 07h /can/trunk/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7578d 04h /can/trunk/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7578d 04h /can/trunk/rtl/verilog/
115 Artisan ram instances added. simons 7583d 22h /can/trunk/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7610d 22h /can/trunk/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7612d 22h /can/trunk/rtl/verilog/
110 Fixed according to the linter. mohor 7612d 23h /can/trunk/rtl/verilog/

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