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[/] [can/] [trunk/] [sim/] [rtl_sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5534d 21h /can/trunk/sim/rtl_sim/
159 *** empty log message *** igorm 6872d 04h /can/trunk/sim/rtl_sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7297d 00h /can/trunk/sim/rtl_sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7521d 19h /can/trunk/sim/rtl_sim/
119 Artisan RAMs added. mohor 7563d 06h /can/trunk/sim/rtl_sim/
48 Actel APA ram supported. mohor 7734d 17h /can/trunk/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7749d 20h /can/trunk/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7754d 22h /can/trunk/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7755d 14h /can/trunk/sim/rtl_sim/
25 *** empty log message *** mohor 7760d 02h /can/trunk/sim/rtl_sim/
24 backup. mohor 7764d 15h /can/trunk/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7780d 03h /can/trunk/sim/rtl_sim/
16 rx_fifo is now working. mohor 7781d 04h /can/trunk/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7785d 18h /can/trunk/sim/rtl_sim/
13 Temporary files (backup). mohor 7786d 02h /can/trunk/sim/rtl_sim/
11 Acceptance filter added. mohor 7787d 14h /can/trunk/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7800d 00h /can/trunk/sim/rtl_sim/
5 Synchronization working. mohor 7801d 02h /can/trunk/sim/rtl_sim/
4 Dir keeper. mohor 7806d 00h /can/trunk/sim/rtl_sim/
2 Initial mohor 7806d 00h /can/trunk/sim/rtl_sim/

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