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[/] - Rev 150

Rev	Log message	Author	Age	Path
150	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7135d 19h	/
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7135d 19h	/
148	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7138d 02h	/
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7138d 02h	/
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7138d 07h	/
145	Arbitration bug fixed.	igorm	7138d 07h	/
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7284d 23h	/
143	Bit acceptance_filter_mode was inverted.	igorm	7284d 23h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7303d 22h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7303d 22h	/
140	I forgot to thange one signal name.	igorm	7358d 20h	/
139	Signal bus_off_on added.	igorm	7358d 21h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7397d 23h	/
137	Header changed.	mohor	7397d 23h	/
136	Error counters changed.	mohor	7397d 23h	/
135	Header changed.	mohor	7398d 00h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7505d 21h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7512d 08h	/
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7512d 08h	/
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7512d 08h	/