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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [cic_d.sv] - Rev 9

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Rev Log message Author Age Path
9 rounding error in the integrator was fixed
code commenting
Juzujka 1709d 18h /cic_core_2/trunk/rtl/verilog/cic_d.sv
7 Bits width of stages was fixed. No overflow occurs now. Juzujka 1712d 13h /cic_core_2/trunk/rtl/verilog/cic_d.sv
6 fixed include for cic_functions Juzujka 1719d 12h /cic_core_2/trunk/rtl/verilog/cic_d.sv
5 directories moved from trunk to root Juzujka 1719d 15h /cic_core_2/trunk/rtl/verilog/cic_d.sv
4 conflict resolving Juzujka 1719d 17h /cic_core_2/trunk/rtl/verilog/cic_d.sv

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