URL https://opencores.org/ocsvn/cop/cop/trunk

Subversion Repositories cop

[/] [cop/] [trunk/] [rtl/] [verilog/] - Rev 12

Rev	Log message	Author	Age	Path
12	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5214d 00h	/cop/trunk/rtl/verilog/
9	Removed unused pin cnt_flag_o from cop_regs.v	rehayes	5422d 01h	/cop/trunk/rtl/verilog/
8	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5422d 01h	/cop/trunk/rtl/verilog/
2	Initial Release June 16, 2009 - Bob Hayes	rehayes	5439d 00h	/cop/trunk/rtl/verilog/