URL https://opencores.org/ocsvn/cop/cop/trunk

Subversion Repositories cop

[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_wb_bus.v] - Rev 13

Rev	Log message	Author	Age	Path
12	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5211d 19h	/cop/trunk/rtl/verilog/cop_wb_bus.v
8	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5419d 20h	/cop/trunk/rtl/verilog/cop_wb_bus.v
2	Initial Release June 16, 2009 - Bob Hayes	rehayes	5436d 19h	/cop/trunk/rtl/verilog/cop_wb_bus.v