URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [TO_DO_list.txt] - Rev 26

Rev	Log message	Author	Age	Path
26	v1.4 PRODUCTION	fpga_is_funny	2053d 18h	/cpu6502_true_cycle/trunk/TO_DO_list.txt
24	Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by simulation with RTI and in a real environment by customer. Removed directory ./verilog_TRIAL from source.	fpga_is_funny	5159d 18h	/cpu6502_true_cycle/trunk/TO_DO_list.txt
18	New directory structure.	root	5530d 19h	/cpu6502_true_cycle/trunk/TO_DO_list.txt
15	CORRECTED "RTI" (wrong: use of stack pointer) RENAME all states of "FSM Execution Unit" for better reading (90%) Finish working for Specification of cpu6502_tc	fpga_is_funny	5542d 21h	/trunk/TO_DO_list.txt
7	This commit was generated by cvs2svn to compensate for changes in r6, which included commits to RCS files with non-trunk default branches.	fpga_is_funny	5594d 18h	/trunk/TO_DO_list.txt
6	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP "JMP (indirect)" produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead $02FF and $0300)	fpga_is_funny	5594d 18h	/trunk/TO_DO_list.txt
2	First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now.	fpga_is_funny	5865d 19h	/trunk/TO_DO_list.txt