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[/] [cpu65c02_true_cycle/] [trunk/] [TO_DO_list.txt] - Rev 18

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18 RELEASE CANDIDATE V1.5 RC of r65c02_tc.
Major Bug Fixes are available.
Look at the header of r65c02_tc.vhd to get more details.
Because of translation errors made by a third party conversion tool in the past, Verilog sources are no longer available. May be re-activated in the future.

The upcoming PRODUCTION version will be include some enhancements for speed and resource utilization.
fpga_is_funny 3941d 16h /cpu65c02_true_cycle/trunk/TO_DO_list.txt
15 New directory structure. root 5548d 04h /cpu65c02_true_cycle/trunk/TO_DO_list.txt
12 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)
fpga_is_funny 5560d 06h /trunk/TO_DO_list.txt
7 - Delete unused nets and blocks (same as R6502_TC)
- Rename blocks
- Re-arrage FSM symbols in block FSM_Execution_Unit
fpga_is_funny 5612d 01h /trunk/TO_DO_list.txt
5 This commit was generated by cvs2svn to compensate for changes in r4, which
included commits to RCS files with non-trunk default branches.
fpga_is_funny 5646d 07h /trunk/TO_DO_list.txt
4 no message fpga_is_funny 5646d 07h /trunk/TO_DO_list.txt
2 loading source files "rtl" and "doc" STATE is BETA. fpga_is_funny 5764d 04h /trunk/TO_DO_list.txt

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