OpenCores
URL https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk

Subversion Repositories cpu65c02_true_cycle

[/] - Rev 17

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 Added old uploaded documents to new repository. root 5531d 12h /
16 Added old uploaded documents to new repository. root 5532d 05h /
15 New directory structure. root 5532d 05h /
14 Obsolete file fpga_is_funny 5536d 02h /
13 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)		 fpga_is_funny 5544d 06h /
12 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)		 fpga_is_funny 5544d 07h /
11 no message fpga_is_funny 5596d 02h /
10 no message fpga_is_funny 5596d 02h /
9 no message fpga_is_funny 5596d 02h /
8 no message fpga_is_funny 5596d 02h /
7 - Delete unused nets and blocks (same as R6502_TC)
- Rename blocks
- Re-arrage FSM symbols in block FSM_Execution_Unit		 fpga_is_funny 5596d 02h /
6 This commit was manufactured by cvs2svn to create tag 'arelease'. 5630d 08h /
5 This commit was generated by cvs2svn to compensate for changes in r4, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5630d 08h /
4 no message fpga_is_funny 5630d 08h /
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5748d 06h /
2 loading source files "rtl" and "doc" STATE is BETA. fpga_is_funny 5748d 06h /
1 Standard project directories initialized by cvs2svn. 5748d 06h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.