URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5536d 10h	/dbg_interface/tags/highland_ver1/
133	This commit was manufactured by cvs2svn to create tag 'highland_ver1'.		7358d 12h	/tags/highland_ver1/
132	Documentation updated. Many missing things added.	igorm	7358d 12h	/trunk/
131	Documentation updated. Many missing things added.	igorm	7358d 13h	/trunk/
129	New documentation.	mohor	7400d 12h	/trunk/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7402d 19h	/trunk/
126	run_sim.scr renamed to run_sim for VATS.	mohor	7405d 19h	/trunk/
124	Display for VATS added.	mohor	7407d 16h	/trunk/
123	All flipflops are reset.	mohor	7407d 16h	/trunk/
121	Port signals are all set to zero after reset.	mohor	7410d 16h	/trunk/
120	test stall_test added.	mohor	7410d 19h	/trunk/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7410d 20h	/trunk/
117	Define name changed.	mohor	7412d 15h	/trunk/
116	Data latching changed when testing WB.	mohor	7412d 16h	/trunk/
115	More debug data added.	mohor	7412d 19h	/trunk/
114	CRC generation iand verification in bench changed.	mohor	7412d 21h	/trunk/
113	IDCODE test improved.	mohor	7412d 22h	/trunk/
112	dbg_tb_defines.v not used.	mohor	7413d 16h	/trunk/
111	Define tap_defines.v added to test bench.	mohor	7413d 17h	/trunk/
110	Waiting for "ready" improved.	mohor	7413d 17h	/trunk/