URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_17/] [bench/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5548d 18h	/dbg_interface/tags/rel_17/bench/
122	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7423d 00h	/dbg_interface/tags/rel_17/bench/
121	Port signals are all set to zero after reset.	mohor	7423d 00h	/dbg_interface/tags/rel_17/bench/
120	test stall_test added.	mohor	7423d 03h	/dbg_interface/tags/rel_17/bench/
117	Define name changed.	mohor	7425d 00h	/dbg_interface/tags/rel_17/bench/
116	Data latching changed when testing WB.	mohor	7425d 00h	/dbg_interface/tags/rel_17/bench/
115	More debug data added.	mohor	7425d 04h	/dbg_interface/tags/rel_17/bench/
114	CRC generation iand verification in bench changed.	mohor	7425d 05h	/dbg_interface/tags/rel_17/bench/
113	IDCODE test improved.	mohor	7425d 06h	/dbg_interface/tags/rel_17/bench/
112	dbg_tb_defines.v not used.	mohor	7426d 01h	/dbg_interface/tags/rel_17/bench/
111	Define tap_defines.v added to test bench.	mohor	7426d 01h	/dbg_interface/tags/rel_17/bench/
110	Waiting for "ready" improved.	mohor	7426d 01h	/dbg_interface/tags/rel_17/bench/
102	New version.	mohor	7427d 20h	/dbg_interface/tags/rel_17/bench/
101	Almost finished.	mohor	7427d 21h	/dbg_interface/tags/rel_17/bench/
99	cpu registers added.	mohor	7428d 23h	/dbg_interface/tags/rel_17/bench/
96	Working.	mohor	7430d 03h	/dbg_interface/tags/rel_17/bench/
95	Temp version.	mohor	7430d 15h	/dbg_interface/tags/rel_17/bench/
93	tmp version.	mohor	7432d 03h	/dbg_interface/tags/rel_17/bench/
92	temp version.	mohor	7435d 06h	/dbg_interface/tags/rel_17/bench/
91	tmp version.	mohor	7436d 01h	/dbg_interface/tags/rel_17/bench/