URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_23/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5536d 15h	/dbg_interface/tags/rel_23/
148	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7336d 21h	/tags/rel_23/
147	CPU_WR_CTRL and CPU_RD_CTRL defines changed.	igorm	7336d 21h	/trunk/
146	Changes for the FormalPRO.	igorm	7340d 18h	/trunk/
145	Support for 2 CPUs added.	igorm	7340d 22h	/trunk/
144	Port names and defines for the supported CPUs changed.	igorm	7340d 23h	/trunk/
143	Signals for easier debugging removed.	igorm	7341d 01h	/trunk/
142	Typo fixed.	igorm	7341d 01h	/trunk/
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7341d 20h	/trunk/
140	CRC checking of incoming CRC added to all tasks.	igorm	7342d 12h	/trunk/
139	New release of the debug interface (3rd. release).	igorm	7344d 14h	/trunk/
138	Temp version before changing dbg interface.	igorm	7350d 18h	/trunk/
136	Table describing chain codes added.	igorm	7354d 19h	/trunk/
135	'hz changed to 1'hz because Icarus complains.	igorm	7357d 19h	/trunk/
132	Documentation updated. Many missing things added.	igorm	7358d 17h	/trunk/
131	Documentation updated. Many missing things added.	igorm	7358d 18h	/trunk/
129	New documentation.	mohor	7400d 17h	/trunk/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7403d 00h	/trunk/
126	run_sim.scr renamed to run_sim for VATS.	mohor	7406d 00h	/trunk/
124	Display for VATS added.	mohor	7407d 21h	/trunk/