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[/] [dbg_interface/] [tags/] [rev_11/] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5537d 03h	/dbg_interface/tags/rev_11/
79	This commit was manufactured by cvs2svn to create tag 'rev_11'.		7502d 05h	/tags/rev_11/
77	MBIST chain connection fixed.	mohor	7502d 05h	/trunk/
75	Simulation files.	mohor	7502d 06h	/trunk/
74	Removed.	mohor	7502d 06h	/trunk/
73	CRC logic changed.	mohor	7502d 07h	/trunk/
71	Mbist support added.	simons	7504d 13h	/trunk/
70	A pdf copy of existing doc document.	simons	7511d 15h	/trunk/
69	WBCNTL added, multiple CPU support described.	simons	7532d 04h	/trunk/
67	Lower two address lines must be always zero.	simons	7537d 09h	/trunk/
65	WB_CNTL register added, some syncronization fixes.	simons	7538d 08h	/trunk/
63	Three more chains added for cpu debug access.	simons	7558d 09h	/trunk/
61	Lapsus fixed.	simons	7586d 09h	/trunk/
59	Reset value for riscsel register set to 1.	simons	7586d 09h	/trunk/
57	Multiple cpu support added.	simons	7586d 11h	/trunk/
56	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7853d 07h	/trunk/
55	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7853d 07h	/trunk/
53	Trst active high. Inverted on higher layer.	mohor	7853d 08h	/trunk/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7853d 09h	/trunk/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7880d 20h	/trunk/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rev_11/] - Rev 158

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