URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5542d 18h	/dbg_interface/trunk/bench/
145	Support for 2 CPUs added.	igorm	7347d 01h	/trunk/bench/
142	Typo fixed.	igorm	7347d 04h	/trunk/bench/
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7347d 23h	/trunk/bench/
140	CRC checking of incoming CRC added to all tasks.	igorm	7348d 15h	/trunk/bench/
139	New release of the debug interface (3rd. release).	igorm	7350d 17h	/trunk/bench/
138	Temp version before changing dbg interface.	igorm	7356d 21h	/trunk/bench/
135	'hz changed to 1'hz because Icarus complains.	igorm	7363d 22h	/trunk/bench/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7409d 03h	/trunk/bench/
124	Display for VATS added.	mohor	7414d 00h	/trunk/bench/
121	Port signals are all set to zero after reset.	mohor	7417d 00h	/trunk/bench/
120	test stall_test added.	mohor	7417d 03h	/trunk/bench/
117	Define name changed.	mohor	7418d 23h	/trunk/bench/
116	Data latching changed when testing WB.	mohor	7419d 00h	/trunk/bench/
115	More debug data added.	mohor	7419d 03h	/trunk/bench/
114	CRC generation iand verification in bench changed.	mohor	7419d 05h	/trunk/bench/
113	IDCODE test improved.	mohor	7419d 06h	/trunk/bench/
112	dbg_tb_defines.v not used.	mohor	7420d 00h	/trunk/bench/
111	Define tap_defines.v added to test bench.	mohor	7420d 01h	/trunk/bench/
110	Waiting for "ready" improved.	mohor	7420d 01h	/trunk/bench/