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URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] - Rev 7

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Rev Log message Author Age Path
7 Fix CL,CWL and AL parameter slai 4517d 06h /ddr3_synthesizable_bfm/trunk/rtl/
6 Added Mode Register Value dump slai 4517d 06h /ddr3_synthesizable_bfm/trunk/rtl/
5 Removed some wrongly checked in backup files slai 4517d 13h /ddr3_synthesizable_bfm/trunk/rtl/
4 Added debug message for MR0 slai 4517d 13h /ddr3_synthesizable_bfm/trunk/rtl/
3 Added ability to handle up to 8 opened bank & uses DM signals slai 4518d 14h /ddr3_synthesizable_bfm/trunk/rtl/
2 Initial Check In slai 4518d 14h /ddr3_synthesizable_bfm/trunk/rtl/

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