URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [ddr3_simple4.v] - Rev 7

Rev	Log message	Author	Age	Path
7	Fix CL,CWL and AL parameter	slai	4518d 21h	/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v
6	Added Mode Register Value dump	slai	4518d 22h	/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v
4	Added debug message for MR0	slai	4519d 04h	/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v
3	Added ability to handle up to 8 opened bank & uses DM signals	slai	4520d 06h	/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v
2	Initial Check In	slai	4520d 06h	/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v