URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

[/] [debouncer_vhdl/] [trunk/] [bench/] - Rev 10

Rev	Log message	Author	Age	Path
10	v1.01.0030: changed internal counter range to (CNT_VAL+1) to avoid adder flip-over.	jdoin	4610d 07h	/debouncer_vhdl/trunk/bench/
9	Clarified the licensing. Added SVN directory for the license text. Changed the LGPL url at the rtl code header. Included the LGPL 3.0 text "lgpl.txt"	jdoin	4630d 11h	/debouncer_vhdl/trunk/bench/
8	Updated verification circuit and comments.	jdoin	4644d 23h	/debouncer_vhdl/trunk/bench/
7	- Changed verification project to have all debug signals to fit on a 16 digital signals for the Tek MSO2014 scope. - Added scope photos of verified circuit	jdoin	4649d 01h	/debouncer_vhdl/trunk/bench/
6	- fixed some minor comments errors; - added ISE report files; - added generated bitgen file (zipped) to test in the Digilent Atlys board;	jdoin	4649d 21h	/debouncer_vhdl/trunk/bench/
5	cleaned-up XISE files	jdoin	4650d 01h	/debouncer_vhdl/trunk/bench/
4	v1.01.0026 [JD]: - removed remnants of SPI_MASTER_SLAVE project from ISE project files. - added pinlock constraint for strobe output for FPGA test.	jdoin	4650d 02h	/debouncer_vhdl/trunk/bench/
3	v1.01.0025 [JD]: - added a pipeline delay for new data strobe output. - included a complete verification project, for simulation and FPGA verification.	jdoin	4650d 02h	/debouncer_vhdl/trunk/bench/
2	v1.00.0020 [JD]: vhdl file for the debouncer loaded. No simulation testbench yet. The file debouncer_vhdl/trunk/rtl/grp_debouncer.vhd is tested and verified in hardware.	jdoin	4650d 12h	/debouncer_vhdl/trunk/bench/