URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys.ucf] - Rev 7

Rev	Log message	Author	Age	Path
7	- Changed verification project to have all debug signals to fit on a 16 digital signals for the Tek MSO2014 scope. - Added scope photos of verified circuit	jdoin	4654d 04h	/debouncer_vhdl/trunk/bench/debounce_atlys.ucf
4	v1.01.0026 [JD]: - removed remnants of SPI_MASTER_SLAVE project from ISE project files. - added pinlock constraint for strobe output for FPGA test.	jdoin	4655d 05h	/debouncer_vhdl/trunk/bench/debounce_atlys.ucf
3	v1.01.0025 [JD]: - added a pipeline delay for new data strobe output. - included a complete verification project, for simulation and FPGA verification.	jdoin	4655d 05h	/debouncer_vhdl/trunk/bench/debounce_atlys.ucf