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[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top_summary.html] - Rev 10

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10 v1.01.0030: changed internal counter range to (CNT_VAL+1) to avoid adder flip-over. jdoin 4615d 07h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
9 Clarified the licensing.
Added SVN directory for the license text.
Changed the LGPL url at the rtl code header.
Included the LGPL 3.0 text "lgpl.txt"		 jdoin 4635d 11h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
8 Updated verification circuit and comments. jdoin 4649d 23h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
7 - Changed verification project to have all debug signals to fit on a 16 digital signals for the Tek MSO2014 scope.
- Added scope photos of verified circuit		 jdoin 4654d 01h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
6 - fixed some minor comments errors;
- added ISE report files;
- added generated bitgen file (zipped) to test in the Digilent Atlys board;		 jdoin 4654d 21h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
5 cleaned-up XISE files jdoin 4655d 01h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
4 v1.01.0026 [JD]:
- removed remnants of SPI_MASTER_SLAVE project from ISE project files.
- added pinlock constraint for strobe output for FPGA test.		 jdoin 4655d 01h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
3 v1.01.0025 [JD]:
- added a pipeline delay for new data strobe output.
- included a complete verification project, for simulation and FPGA verification.		 jdoin 4655d 02h /debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html

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