URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_vhdl_bench.gise] - Rev 10

Rev	Log message	Author	Age	Path
10	v1.01.0030: changed internal counter range to (CNT_VAL+1) to avoid adder flip-over.	jdoin	4603d 21h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
9	Clarified the licensing. Added SVN directory for the license text. Changed the LGPL url at the rtl code header. Included the LGPL 3.0 text "lgpl.txt"	jdoin	4624d 01h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
8	Updated verification circuit and comments.	jdoin	4638d 13h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
7	- Changed verification project to have all debug signals to fit on a 16 digital signals for the Tek MSO2014 scope. - Added scope photos of verified circuit	jdoin	4642d 14h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
6	- fixed some minor comments errors; - added ISE report files; - added generated bitgen file (zipped) to test in the Digilent Atlys board;	jdoin	4643d 11h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
4	v1.01.0026 [JD]: - removed remnants of SPI_MASTER_SLAVE project from ISE project files. - added pinlock constraint for strobe output for FPGA test.	jdoin	4643d 15h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
3	v1.01.0025 [JD]: - added a pipeline delay for new data strobe output. - included a complete verification project, for simulation and FPGA verification.	jdoin	4643d 15h	/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise