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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] - Rev 333

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Rev Log message Author Age Path
333 update TODO hellwig 2744d 07h /
332 update COPYING hellwig 2805d 08h /
331 machine monitor: init kbd and dsp only if explicitly requested hellwig 2805d 21h /
330 sim/getline/testgl.c: return type of main() changed to int hellwig 2805d 22h /
329 lcc/lburg/gram.y: prototype for yylex() added hellwig 2805d 22h /
328 lcc/etc/lcc.c: return type of main() changed to int hellwig 2805d 22h /
327 flag -m32 in compilation of vcdchk deleted hellwig 3073d 08h /
326 RAM simulation access times set to realistic values hellwig 3184d 03h /
325 memory speed measurement for new controller added hellwig 3192d 18h /
324 README updated hellwig 3192d 19h /
323 memspeed renamed to memspeed-1 hellwig 3192d 19h /
322 README updated, Makefile added hellwig 3193d 06h /
321 README updated hellwig 3193d 07h /
320 README updated hellwig 3194d 03h /
319 memory controller 2, FPGA realization hellwig 3194d 08h /
318 memory controller 1, FPGA realization hellwig 3194d 08h /
317 README updated hellwig 3194d 23h /
316 README added hellwig 3195d 02h /
315 README added hellwig 3195d 02h /
314 memory controller simulation 2 hellwig 3195d 04h /
313 memory controller simulation 1 hellwig 3195d 06h /
312 memory controller simulation 0 hellwig 3195d 07h /
311 README updated hellwig 3195d 08h /
310 verilated mc implementation with and without trace hellwig 3196d 04h /
309 multicycle simulation of ECO32, using Verilator hellwig 3197d 05h /
308 multicycle design, suitable for being verilated hellwig 3197d 09h /
307 several tests got duration.dat files hellwig 3197d 22h /
306 tool to show display output added hellwig 3198d 06h /
305 tool to show serial output added hellwig 3198d 06h /
304 Makefile updated hellwig 3200d 17h /

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