URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] - Rev 332

Rev	Log message	Author	Age	Path
326	RAM simulation access times set to realistic values	hellwig	3184d 01h	/eco32/trunk/fpga/
325	memory speed measurement for new controller added	hellwig	3192d 16h	/eco32/trunk/fpga/
324	README updated	hellwig	3192d 17h	/eco32/trunk/fpga/
323	memspeed renamed to memspeed-1	hellwig	3192d 17h	/eco32/trunk/fpga/
322	README updated, Makefile added	hellwig	3193d 05h	/eco32/trunk/fpga/
321	README updated	hellwig	3193d 05h	/eco32/trunk/fpga/
320	README updated	hellwig	3194d 01h	/eco32/trunk/fpga/
319	memory controller 2, FPGA realization	hellwig	3194d 06h	/eco32/trunk/fpga/
318	memory controller 1, FPGA realization	hellwig	3194d 06h	/eco32/trunk/fpga/
317	README updated	hellwig	3194d 21h	/eco32/trunk/fpga/
316	README added	hellwig	3195d 00h	/eco32/trunk/fpga/
315	README added	hellwig	3195d 00h	/eco32/trunk/fpga/
314	memory controller simulation 2	hellwig	3195d 02h	/eco32/trunk/fpga/
313	memory controller simulation 1	hellwig	3195d 04h	/eco32/trunk/fpga/
312	memory controller simulation 0	hellwig	3195d 05h	/eco32/trunk/fpga/
311	README updated	hellwig	3195d 06h	/eco32/trunk/fpga/
310	verilated mc implementation with and without trace	hellwig	3196d 02h	/eco32/trunk/fpga/
309	multicycle simulation of ECO32, using Verilator	hellwig	3197d 03h	/eco32/trunk/fpga/
308	multicycle design, suitable for being verilated	hellwig	3197d 07h	/eco32/trunk/fpga/
307	several tests got duration.dat files	hellwig	3197d 20h	/eco32/trunk/fpga/