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Rev Log message Author Age Path
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6756d 12h /
99 Document revised. mohor 6763d 11h /
98 Document revised. mohor 6763d 11h /
97 Small typo fixed. lampret 6780d 10h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 6784d 10h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 6784d 13h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 6784d 13h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 6789d 11h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6790d 13h /
91 Comments in Slovene language removed. mohor 6790d 13h /
90 casex changed with case, fifo reset changed. mohor 6790d 13h /
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.
mohor 6794d 11h /
88 rx_fifo was not always cleared ok. Fixed. mohor 6800d 10h /
87 Status was not latched correctly sometimes. Fixed. mohor 6800d 12h /
86 Big Endian problem when sending frames fixed. mohor 6801d 19h /
85 Log info was missing. mohor 6807d 05h /
84 LinkFail signal was not latching appropriate bit. mohor 6807d 05h /
83 MAC address recognition was not correct (bytes swaped). mohor 6807d 05h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 6807d 07h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 6807d 07h /

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