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Rev	Log message	Author	Age	Path
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8033d 20h	/
99	Document revised.	mohor	8040d 19h	/
98	Document revised.	mohor	8040d 20h	/
97	Small typo fixed.	lampret	8057d 18h	/
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8061d 18h	/
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8061d 21h	/
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8061d 21h	/
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8066d 19h	/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8067d 21h	/
91	Comments in Slovene language removed.	mohor	8067d 21h	/
90	casex changed with case, fifo reset changed.	mohor	8067d 21h	/
89	TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description changed.	mohor	8071d 19h	/
88	rx_fifo was not always cleared ok. Fixed.	mohor	8077d 18h	/
87	Status was not latched correctly sometimes. Fixed.	mohor	8077d 20h	/
86	Big Endian problem when sending frames fixed.	mohor	8079d 03h	/
85	Log info was missing.	mohor	8084d 13h	/
84	LinkFail signal was not latching appropriate bit.	mohor	8084d 13h	/
83	MAC address recognition was not correct (bytes swaped).	mohor	8084d 13h	/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8084d 15h	/
81	Typos fixed, INT_SOURCE and INT_MASK registers changed.	mohor	8084d 15h	/

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