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Rev Log message Author Age Path
84 LinkFail signal was not latching appropriate bit. mohor 8098d 23h /
83 MAC address recognition was not correct (bytes swaped). mohor 8098d 23h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8099d 01h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8099d 01h /
80 Small fixes for external/internal DMA missmatches. mohor 8103d 03h /
79 RetryCntLatched was unused and removed from design mohor 8103d 04h /
78 WB_SEL_I was unused and removed from design mohor 8103d 04h /
77 Interrupts changed mohor 8103d 04h /
76 Interrupts changed in the top file mohor 8103d 04h /
75 r_Bro is used for accepting/denying frames mohor 8103d 04h /

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