Subversion Repositories ethmac

[/] - Rev 111


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
111 Master state machine had a bug when switching from master write to
master read.
mohor 6648d 18h /
110 m_wb_cyc_o signal released after every single transfer. mohor 6648d 21h /
109 Comment removed. mohor 6648d 22h /
108 Testbench supports unaligned accesses. mohor 6716d 07h /
107 TX_BUF_BASE changed. mohor 6716d 07h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6716d 08h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6725d 09h /
104 FCS should not be included in NibbleMinFl. mohor 6727d 03h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6727d 04h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6727d 04h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6727d 04h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6727d 04h /
99 Document revised. mohor 6734d 03h /
98 Document revised. mohor 6734d 03h /
97 Small typo fixed. lampret 6751d 01h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 6755d 01h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 6755d 04h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 6755d 04h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 6760d 03h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 6761d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.